Lint summary
Lint summary
Unconnected/logic driven clocks 0
Sequential data pins driven by a clock signal 0
Sequential clock pins without clock waveform 0
Sequential clock pins with multiple clock waveforms 0
Generated clocks without clock waveform 0
Generated clocks with incompatible options 0
Generated clocks with multi-master clock 0
Paths constrained with different clocks 0
Loop-breaking cells for combinational feedback 0
Nets with multiple drivers 0
Timing exceptions with no effect 1
Suspicious multi_cycle exceptions 0
Pins/ports with conflicting case constants 0
Inputs without clocked external delays 0
Outputs without clocked external delays 0
Inputs without external driver/transition 0
Outputs without external load 0
Exceptions with invalid timing start-/endpoints 0
Total: 1
1. Unconnected/logic driven clocks — 0
Meaning:
Clocks in your design should be driven by a dedicated clock source (like a PLL or oscillator) and connected properly. If a clock signal is not connected or driven by logic gates instead of a proper clock source, it can cause timing analysis issues.
Example:
wire clk;
assign clk = a & b; // Clock driven by logic (not recommended)
This is flagged because a clock should not be generated by combinational logic like AND gates.
2. Sequential data pins driven by a clock signal — 0
Meaning:
Input data pins to sequential elements (flip-flops) should not be driven directly by a clock signal. Data inputs should be valid data, not clocks.
Example:
always @(posedge clk) begin
dff <= clk; // wrong: data driven by clock signal itself
end
Here, the data input is connected to the clock, which is wrong.
3. Sequential clock pins without clock waveform — 0
Meaning:
Clock pins of sequential elements (like FFs) should have defined clock waveforms (timing info). If the timing tool doesn’t have waveform info, it cannot analyze timing properly.
Example:
If your constraints miss defining the clock waveform (like period, duty cycle), the tool flags this.
4. Sequential clock pins with multiple clock waveforms — 0
Meaning:
A single clock pin should have one clock waveform definition. Multiple conflicting clock waveforms can confuse timing analysis.
Example:
If you define the clock period twice with different values for the same clock, you get this warning.
5. Generated clocks without clock waveform — 0
Meaning:
Clocks generated inside the design (e.g., from clock dividers) must have timing waveforms defined for the tool.
Example:
If a clock divider generates a clock but no period or waveform is provided, this flag occurs.
6. Generated clocks with incompatible options — 0
Meaning:
Generated clocks might have conflicting properties (like phase, duty cycle) that don’t match the source clock.
Example:
If a generated clock is defined with a 50% duty cycle but source clock is 30%, or if phase shift definitions contradict.
7. Generated clocks with multi-master clock — 0
Meaning:
A generated clock should have a single master clock source. If multiple clocks try to drive the same generated clock net, it causes ambiguity.
8. Paths constrained with different clocks — 0
Meaning:
A timing path should be constrained with one clock domain. If different constraints specify different clocks on the same path, it’s a problem.
9. Loop-breaking cells for combinational feedback — 0
Meaning:
Combinational loops (feedback paths without registers) are illegal in synchronous design. Loop-breaking cells are inserted to avoid infinite loops during timing analysis.
10. Nets with multiple drivers — 0
Meaning:
A net (wire) should have only one driver. Multiple drivers cause conflicts and possible glitches.
Example:
assign a = b;
assign a = c; // two drivers for a
This causes multiple drivers.
11. Timing exceptions with no effect — 1
Meaning:
Timing exceptions (like false paths, multicycle paths) defined in constraints but not affecting any timing paths. This is a warning to clean up unnecessary constraints.
Example:
If you declare a false path between two signals but no path exists, it’s flagged.
12. Suspicious multi_cycle exceptions — 0
Meaning:
multi-cycle paths allow more than one clock cycle for data to propagate. Suspicious ones may be incorrectly defined or inconsistent.
13. Pins/ports with conflicting case constants — 0
Meaning:
Pins or ports defined with conflicting constant logic levels (e.g., input tied to 0 in one place and 1 in another) cause issues.
14. Inputs without clocked external delays — 0
Meaning:
External input delays specify timing for signals coming from outside the chip. Missing delays for inputs can reduce accuracy of timing analysis.
15. Outputs without clocked external delays — 0
Meaning:
Outputs should also have delays defined to model external load or environment.
16. Inputs without external driver/transition — 0
Meaning:
Input pins must have driver and transition info defined to simulate realistic timing.
17. Outputs without external load — 0
Meaning:
Outputs should have defined load capacitance or equivalent for proper timing.
18. Exceptions with invalid timing start-/endpoints — 0
Meaning:
Timing exceptions (like false paths) must have valid start and end points in constraints. If invalid, they are ignored or flagged.
Code Snippets for each:
1. Unconnected/logic driven clocks
Verilog (bad clock driven by logic):
wire clk;
assign clk = a & b; // Clock driven by logic - bad practice
2. Sequential data pins driven by a clock signal
Verilog (wrong data input driven by clock):
always @(posedge clk) begin
q <= clk; // data input driven by clock signal - incorrect
end
3. Sequential clock pins without clock waveform
SDC (missing waveform info):
create_clock -name clk -period 10 [get_ports clk]
// No waveform specified, causes issue in some tools
Correct with waveform:
create_clock -name clk -period 10 -waveform {0 5} [get_ports clk]
4. Sequential clock pins with multiple clock waveforms
SDC (conflicting clocks on same port):
create_clock -name clk -period 10 -waveform {0 5} [get_ports clk]
create_clock -name clk -period 8 -waveform {0 4} [get_ports clk] # Conflicts
5. Generated clocks without clock waveform
SDC (missing waveform for generated clock):
create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 [get_pins clk_div2]
// Missing waveform option leads to warning
Correct:
create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 -waveform {0 10} [get_pins clk_div2]
6. Generated clocks with incompatible options
SDC (conflicting duty cycles):
create_clock -name clk -period 10 -waveform {0 4} [get_ports clk] # 40% duty
create_generated_clock -name gen_clk -source [get_ports clk] -multiply_by 1 -divide_by 1 -waveform {0 5} [get_pins gen_clk] # 50% duty -> conflict
7. Generated clocks with multi-master clock
SDC (generated clock driven by multiple clocks):
create_generated_clock -name gen_clk -source [get_ports clk1] [get_pins gen_clk]
create_generated_clock -name gen_clk -source [get_ports clk2] [get_pins gen_clk] # Multi-master source
8. Paths constrained with different clocks
SDC (conflicting constraints on same path):
set_multicycle_path -setup 2 -from [get_clocks clk1] -to [get_clocks clk1]
set_multicycle_path -setup 1 -from [get_clocks clk2] -to [get_clocks clk1] # Conflicts on same path
9. Loop-breaking cells for combinational feedback
Verilog (combinational loop example):
wire a;
assign a = ~a; // Combinational feedback loop, illegal
Loop-breaking cell (special flip-flop or latch inserted manually or by tool) is required to break this.
10. Nets with multiple drivers
Verilog (multiple drivers):
wire a;
assign a = b;
assign a = c; // Multiple drivers on wire 'a' - illegal
11. Timing exceptions with no effect
SDC (false path that doesn't exist):
set_false_path -from [get_ports non_existing_port] -to [get_ports another_port]
Since the path doesn't exist, this has no effect.
12. Suspicious multi_cycle exceptions
SDC (multi-cycle path with unusual constraints):
set_multicycle_path -setup 0 -from [get_clocks clk] -to [get_clocks clk]
-setup 0 is suspicious because multi-cycle should be >=1.
13. Pins/ports with conflicting case constants
Verilog (conflicting constants):
wire in;
assign in = 1'b0; // Port tied to zero here
// Elsewhere assigned 1'b1 causing conflict
14. Inputs without clocked external delays
SDC (missing input delay):
# No input delay specified for input port 'data_in'
// Add with:
set_input_delay -clock clk 5 [get_ports data_in]
15. Outputs without clocked external delays
SDC (missing output delay):
# No output delay specified for output port 'data_out'
// Add with:
set_output_delay -clock clk 3 [get_ports data_out]
16. Inputs without external driver/transition
SDC (missing transition on inputs):
# No transition specified on input ports
set_driving_cell -lib_cell INV_X1 [get_ports data_in]
set_input_transition 1.0 [get_ports data_in]
17. Outputs without external load
SDC (missing output load):
# No load specified on output ports
set_load 10 [get_ports data_out]
18. Exceptions with invalid timing start-/endpoints
SDC (invalid false path endpoints):
set_false_path -from [get_ports invalid_port] -to [get_ports data_out] # invalid startpoint