set_db write_def_hierarchy_delimiter /
set_db init_netlist_files ../logical_synthesis/outputs_Mar14-02:18:47/apb_timer_m.v
set_db init_lef_files ../logical_synthesis/lib_search_path/gsclib045.fixed2.lef
set_db init_power_nets VDD
set_db init_ground_nets VSS
set_db init_mmmc_files ../mmmc/apb_timer.view
set_db init_power_nets VDD
set_db init_power_nets VDD
set_db init_ground_nets VSS
set_db init_ground_nets VSS
read_mmmc ../mmmc/apb_timer.view
read_physical -lef ../logical_synthesis/lib_search_path/gsclib045.fixed2.lef
read_netlist ../logical_synthesis/outputs_Mar14-02:18:47/apb_timer_m.v
set_current_design {}
init_design
eval_legacy { setLibraryUnit -time none -internal }
set_db floorplan_is_max_io_height 1
set_io_flow_flag 0
create_floorplan -core_density_size 1.0 0.7 0 0 0 0 -flip f
report_resource
report_resource -start {Constraint file reading stats}
get_ports PCLK
report_resource -end {Constraint file reading stats}
report_resource
=============================================================================
create_floorplan -site CoreSite -core_density_size 0.945815835297 0.499997 4 4 4 4
=============================================================================
set_db assign_pins_edit_in_batch 1
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Left -layer 1 -spread_type center -spacing 0.19 -pin {PCLK PCLKG PRESETn PSEL {PADDR[2]} {PADDR[3]} {PADDR[4]} {PADDR[5]} {PADDR[6]} {PADDR[7]} {PADDR[8]} {PADDR[9]} {PADDR[10]} {PADDR[11]} PENABLE {ECOREVNUM[0]} {ECOREVNUM[1]} {ECOREVNUM[2]} {ECOREVNUM[3]} EXTIN}
set_db assign_pins_edit_in_batch 0
set_db assign_pins_edit_in_batch 1
edit_pin -pin_width 0.06 -pin_depth 0.335 -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Left -layer 1 -spread_type center -spacing 0.19 -pin {PCLK PCLKG PRESETn PSEL {PADDR[2]} {PADDR[3]} {PADDR[4]} {PADDR[5]} {PADDR[6]} {PADDR[7]} {PADDR[8]} {PADDR[9]} {PADDR[10]} {PADDR[11]} PENABLE {ECOREVNUM[0]} {ECOREVNUM[1]} {ECOREVNUM[2]} {ECOREVNUM[3]} EXTIN}
set_db assign_pins_edit_in_batch 0
gui_fit
=============================================================================
set_db assign_pins_edit_in_batch 1
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 2 -spread_type center -spacing 0.19 -pin {{PWDATA[0]} {PWDATA[1]} {PWDATA[2]} {PWDATA[3]} {PWDATA[4]} {PWDATA[5]} {PWDATA[6]} {PWDATA[7]} {PWDATA[8]} {PWDATA[9]} {PWDATA[10]} {PWDATA[11]} {PWDATA[12]} {PWDATA[13]} {PWDATA[14]} {PWDATA[15]} {PWDATA[16]} {PWDATA[17]} {PWDATA[18]} {PWDATA[19]} {PWDATA[20]} {PWDATA[21]} {PWDATA[22]} {PWDATA[23]} {PWDATA[24]} {PWDATA[25]} {PWDATA[26]} {PWDATA[27]} {PWDATA[28]} {PWDATA[29]} {PWDATA[30]} {PWDATA[31]}}
set_db assign_pins_edit_in_batch 0
set_db assign_pins_edit_in_batch 1
edit_pin -pin_width 0.07 -pin_depth 0.29 -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 2 -spread_type center -spacing -0.2 -pin {{PWDATA[0]} {PWDATA[1]} {PWDATA[2]} {PWDATA[3]} {PWDATA[4]} {PWDATA[5]} {PWDATA[6]} {PWDATA[7]} {PWDATA[8]} {PWDATA[9]} {PWDATA[10]} {PWDATA[11]} {PWDATA[12]} {PWDATA[13]} {PWDATA[14]} {PWDATA[15]} {PWDATA[16]} {PWDATA[17]} {PWDATA[18]} {PWDATA[19]} {PWDATA[20]} {PWDATA[21]} {PWDATA[22]} {PWDATA[23]} {PWDATA[24]} {PWDATA[25]} {PWDATA[26]} {PWDATA[27]} {PWDATA[28]} {PWDATA[29]} {PWDATA[30]} {PWDATA[31]}}
set_db assign_pins_edit_in_batch 0
=============================================================================
get_ports -filter {direction == out}
set_db assign_pins_edit_in_batch 1
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Right -layer 3 -spread_type center -spacing 1.0 -pin {{PRDATA[0]} {PRDATA[1]} {PRDATA[2]} {PRDATA[3]} {PRDATA[4]} {PRDATA[5]} {PRDATA[6]} {PRDATA[7]} {PRDATA[8]} {PRDATA[9]} {PRDATA[10]} {PRDATA[11]} {PRDATA[12]} {PRDATA[13]} {PRDATA[14]} {PRDATA[15]} {PRDATA[16]} {PRDATA[17]} {PRDATA[18]} {PRDATA[19]} {PRDATA[20]} {PRDATA[21]} {PRDATA[22]} {PRDATA[23]} {PRDATA[24]} {PRDATA[25]} {PRDATA[26]} {PRDATA[27]} {PRDATA[28]} {PRDATA[29]} {PRDATA[30]} {PRDATA[31]} PREADY PSLVERR TIMERINT}
set_db assign_pins_edit_in_batch 0
set_db assign_pins_edit_in_batch 1
edit_pin -pin_width 0.07 -pin_depth 0.29 -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Right -layer 3 -spread_type center -spacing -0.95 -pin {{PRDATA[0]} {PRDATA[1]} {PRDATA[2]} {PRDATA[3]} {PRDATA[4]} {PRDATA[5]} {PRDATA[6]} {PRDATA[7]} {PRDATA[8]} {PRDATA[9]} {PRDATA[10]} {PRDATA[11]} {PRDATA[12]} {PRDATA[13]} {PRDATA[14]} {PRDATA[15]} {PRDATA[16]} {PRDATA[17]} {PRDATA[18]} {PRDATA[19]} {PRDATA[20]} {PRDATA[21]} {PRDATA[22]} {PRDATA[23]} {PRDATA[24]} {PRDATA[25]} {PRDATA[26]} {PRDATA[27]} {PRDATA[28]} {PRDATA[29]} {PRDATA[30]} {PRDATA[31]} PREADY PSLVERR TIMERINT}
set_db assign_pins_edit_in_batch 0
gui_fit
=============================================================================
set_db assign_pins_edit_in_batch 1
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Top -layer 2 -spread_type center -spacing 0.19 -pin PWRITE
set_db assign_pins_edit_in_batch 0
=============================================================================
check_pin_assignment
legalize_pins -pins * -move_fixed_pins
check_pin_assignment
=============================================================================
# Add Rings
set_db add_rings_target default
set_db add_rings_extend_over_row 0
set_db add_rings_ignore_rows 0
set_db add_rings_avoid_short 0
set_db add_rings_skip_shared_inner_ring none
set_db add_rings_stacked_via_top_layer Metal9
set_db add_rings_stacked_via_bottom_layer Metal1
set_db add_rings_via_using_exact_crossover_size 1
set_db add_rings_orthogonal_only 1
set_db add_rings_skip_via_on_pin standardcell
set_db add_rings_skip_via_on_wire_shape noshape
add_rings -nets {VDD VSS} -type core_rings -follow core -layer {top Metal1 bottom Metal1 left Metal2 right Metal2} -width {top 0.5 bottom 0.5 left 0.5 right 0.5} -spacing {top 0.1 bottom 0.1 left 0.15 right 0.15} -offset {top 0.5 bottom 0.5 left 0.5 right 0.5} -center 0 -extend_corners {} -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
=============================================================================
# Add Stripes
set_db add_stripes_ignore_block_check 0
set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only 0
set_db add_stripes_rows_without_stripes_only 0
set_db add_stripes_extend_to_closest_target none
set_db add_stripes_stop_at_last_wire_for_area 0
set_db add_stripes_partial_set_through_domain 0
set_db add_stripes_ignore_non_default_domains 0
set_db add_stripes_trim_antenna_back_to_shape none
set_db add_stripes_spacing_type edge_to_edge
set_db add_stripes_spacing_from_block 0
set_db add_stripes_stripe_min_length stripe_width
set_db add_stripes_stacked_via_top_layer Metal9
set_db add_stripes_stacked_via_bottom_layer Metal1
set_db add_stripes_via_using_exact_crossover_size 0
set_db add_stripes_split_vias 0
set_db add_stripes_orthogonal_only 1
set_db add_stripes_allow_jog {padcore_ring block_ring}
eval_legacy { addStripe -nets {VDD VSS} -layer Metal1 -direction vertical -width 0.5 -spacing 0.1 -number_of_sets 5 -start_from left -switch_layer_over_obs false -max_same_layer_jog_length 2 -padcore_ring_top_layer_limit Metal9 -padcore_ring_bottom_layer_limit Metal1 -block_ring_top_layer_limit Metal9 -block_ring_bottom_layer_limit Metal1 -use_wire_group 0 -snap_wire_center_to_grid None -skip_via_on_pin { standardcell } -skip_via_on_wire_shape { noshape } }
=============================================================================
# Add Special Routes
set_db route_special_via_connect_to_shape noshape
route_special -connect {block_pin pad_pin pad_ring core_pin floating_stripe} -layer_change_range { Metal1(1) Metal9(9) } -block_pin_target {nearest_target} -pad_pin_port_connect {all_port one_geom} -pad_pin_target {nearest_target} -core_pin_target {first_after_row_end} -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -crossover_via_layer_range { Metal1(1) Metal9(9) } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { Metal1(1) Metal9(9) }
=============================================================================
place_opt_design
=============================================================================
write_db place_opt_design
=============================================================================
create_clock_tree_spec
=============================================================================
clock_design
=============================================================================
write_db postCTSopt
=============================================================================
set_db route_design_with_timing_driven 0
set_db route_design_with_si_driven 0
route_design -global_detail
set_db route_design_reserve_space_for_multi_cut 1
set_db route_design_concurrent_minimize_via_count_effort high
get_multi_cpu_usage -local_cpu
get_multi_cpu_usage -cpu_per_remote_host
get_multi_cpu_usage -remote_host
set_db route_design_with_timing_driven 1
set_db route_design_with_si_driven 1
set_db route_design_with_timing_driven 1
set_db route_design_with_si_driven 1
route_design -global_detail
set_db route_design_reserve_space_for_multi_cut 1
set_db route_design_concurrent_minimize_via_count_effort high
set_db route_design_detail_post_route_spread_wire 0.500000
set_db route_design_detail_post_route_spread_wire auto
set_db route_design_with_si_driven 1
set_db route_design_with_timing_driven 1
reset_db route_design_concurrent_minimize_via_count_effort
reset_db route_design_reserve_space_for_multi_cut
reset_db route_design_detail_post_route_spread_wire
delete_drc_markers
=============================================================================
extract_rc
write_parasitics -spef_file apb_timer.spef -rc_corner rccorners
=============================================================================
set_db timing_analysis_type ocv
time_design -post_route
time_design -post_route -hold
=============================================================================
set_db check_implant 1
set_db check_drc_implant_across_rows 0
set_db check_drc_ndr_spacing 0
set_db check_drc_inside_via_def 0
set_db check_drc_exclude_pg_net 0
set_db check_drc_ignore_trial_route 0
set_db check_drc_report apb_timer.drc.rpt
set_db check_drc_limit 1000
check_drc