************************************************************************
* auCdl Netlist:
*
* Library Name: TMSY_18nm
* Top Cell Name: invx1
* View Name: schematic
* Netlisted on: Feb 13 01:17:24 2019
************************************************************************
*.BIPOLAR
*.RESI = 2000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
************************************************************************
* Library Name: TMSY_18nm
* Cell Name: invx1
* View Name: schematic
************************************************************************
simulator lang=spice
.SUBCKT invx1 a vdd vss y
*.PININFO a:I y:O vdd:B vss:B
MPM0 y a vdd vdd cds_ff_mpt_p1hvt m=1 l=18n nfin=2 nf=1
MNM0 y a vss vss cds_ff_mpt_n1hvt m=1 l=18n nfin=2 nf=1
.ENDS
library (TT_25_1.1) {
/* Models written by Liberate dev from Cadence Design Systems, Inc. on Wed Feb 13 01:29:33 IST 2019 */
comment : "";
date : "$Date: Wed Feb 13 01:29:20 2019 $";
revision : "1.0";
delay_model : table_lookup;
capacitive_load_unit (1,pf);
current_unit : "1mA";
leakage_power_unit : "1uW";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
voltage_map (vdd, 1.1);
voltage_map (vss, 0);
voltage_map (vnw, 1.1);
voltage_map (vpw, 0);
voltage_map (GND, 0);
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_max_transition : 0.48;
default_output_pin_cap : 0;
in_place_swap_mode : match_footprint;
input_threshold_pct_fall : 50;
input_threshold_pct_rise : 50;
nom_process : 1;
nom_temperature : 25;
nom_voltage : 1.1;
output_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
slew_derate_from_library : 1;
slew_lower_threshold_pct_fall : 10;
slew_lower_threshold_pct_rise : 10;
slew_upper_threshold_pct_fall : 90;
slew_upper_threshold_pct_rise : 90;
operating_conditions (PVT_1P1V_25C) {
process : 1;
temperature : 25;
voltage : 1.1;
}
default_operating_conditions : PVT_1P1V_25C;
lu_table_template (constraint_template_2x2) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("0.008, 0.28");
index_2 ("0.008, 0.28");
}
lu_table_template (delay_template_2x2) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.3");
}
lu_table_template (mpw_constraint_template_2x2) {
variable_1 : constrained_pin_transition;
index_1 ("0.008, 0.28");
}
power_lut_template (passive_power_template_2x1) {
variable_1 : input_transition_time;
index_1 ("0.008, 0.28");
}
power_lut_template (power_template_2x2) {
variable_1 : input_transition_time;
variable_2 : total_output_net_capacitance;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.3");
}
cell (invx1) {
area : 0;
cell_leakage_power : 0.0110051;
pg_pin (vdd) {
pg_type : primary_power;
voltage_name : "vdd";
}
pg_pin (vss) {
pg_type : primary_ground;
voltage_name : "vss";
}
leakage_power () {
value : 0.00823526;
when : "a";
related_pg_pin : vdd;
}
leakage_power () {
value : 0;
when : "a";
related_pg_pin : vss;
}
leakage_power () {
value : 0.0137749;
when : "!a";
related_pg_pin : vdd;
}
leakage_power () {
value : 0;
when : "!a";
related_pg_pin : vss;
}
leakage_power () {
value : 0.0110051;
related_pg_pin : vdd;
}
leakage_power () {
value : 0;
related_pg_pin : vss;
}
pin (y) {
direction : output;
function : "!a";
power_down_function : "(!vdd) + (vss)";
related_ground_pin : vss;
related_power_pin : vdd;
max_capacitance : 0.0178582;
max_transition : 0.465777;
timing () {
related_pin : "a";
timing_sense : negative_unate;
timing_type : combinational;
cell_rise (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0178582");
values ( \
"0.00835263, 0.220942", \
"0.0476206, 0.341683" \
);
}
rise_transition (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0178582");
values ( \
"0.00820631, 0.412849", \
"0.0800175, 0.465777" \
);
}
cell_fall (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0178582");
values ( \
"0.00663246, 0.161189", \
"0.0136441, 0.283303" \
);
}
fall_transition (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0178582");
values ( \
"0.00563534, 0.286857", \
"0.0781494, 0.360292" \
);
}
}
internal_power () {
related_pin : "a";
related_pg_pin : vdd;
rise_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0178582");
values ( \
"0.000331472, 0.000323194", \
"0.00106457, 0.000525999" \
);
}
fall_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0178582");
values ( \
"-6.18622e-05, -4.79624e-05", \
"0.000642731, 0.000168235" \
);
}
}
internal_power () {
related_pin : "a";
related_pg_pin : vss;
rise_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0178582");
values ( \
"-5.52124e-05, -3.56526e-05", \
"0.000678809, 0.000221361" \
);
}
fall_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0178582");
values ( \
"0.00033039, 0.000319749", \
"0.00103356, 0.000500168" \
);
}
}
}
pin (a) {
direction : input;
related_ground_pin : vss;
related_power_pin : vdd;
max_transition : 0.48;
capacitance : 0.000471865;
rise_capacitance : 0.000474586;
rise_capacitance_range (0.0003115, 0.000640863);
fall_capacitance : 0.000469145;
fall_capacitance_range (0.000315373, 0.000638659);
}
}
}