************************************************************************
* auCdl Netlist:
*
* Library Name: gsclib045_all_v4.7
* Top Cell Name: INVX1
* View Name: schematic
* Netlisted on: Oct 20 17:16:55 2023
************************************************************************
*.BIPOLAR
*.RESI = 2000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
*.GLOBAL VDD
+ VSS
*.PIN VDD
*+ VSS
************************************************************************
* Library Name: gsclib045_all_v4.7
* Cell Name: INVX1
* View Name: schematic
************************************************************************
simulator lang=spice
.SUBCKT INVX1 A Y
*.PININFO A:I Y:O
Mmp0 Y A VDD VDD g45p1svt m=1 l=45n w=390n
Mmn0 Y A VSS VSS g45n1svt m=1 l=45n w=260n
.ENDS
library (TT_25_1.1) {
/* Models written by Liberate dev from Cadence Design Systems, Inc. on Wed Feb 13 01:51:23 IST 2019 */
comment : "";
date : "$Date: Wed Feb 13 01:51:05 2019 $";
revision : "1.0";
delay_model : table_lookup;
capacitive_load_unit (1,pf);
current_unit : "1mA";
leakage_power_unit : "1uW";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
voltage_map (vdd, 1.1);
voltage_map (vss, 0);
voltage_map (vnw, 1.1);
voltage_map (vpw, 0);
voltage_map (GND, 0);
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_max_transition : 0.48;
default_output_pin_cap : 0;
in_place_swap_mode : match_footprint;
input_threshold_pct_fall : 50;
input_threshold_pct_rise : 50;
nom_process : 1;
nom_temperature : 25;
nom_voltage : 1.1;
output_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
slew_derate_from_library : 1;
slew_lower_threshold_pct_fall : 10;
slew_lower_threshold_pct_rise : 10;
slew_upper_threshold_pct_fall : 90;
slew_upper_threshold_pct_rise : 90;
operating_conditions (PVT_1P1V_25C) {
process : 1;
temperature : 25;
voltage : 1.1;
}
default_operating_conditions : PVT_1P1V_25C;
lu_table_template (constraint_template_2x2) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("0.008, 0.28");
index_2 ("0.008, 0.28");
}
lu_table_template (delay_template_2x2) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.3");
}
lu_table_template (mpw_constraint_template_2x2) {
variable_1 : constrained_pin_transition;
index_1 ("0.008, 0.28");
}
power_lut_template (passive_power_template_2x1) {
variable_1 : input_transition_time;
index_1 ("0.008, 0.28");
}
power_lut_template (power_template_2x2) {
variable_1 : input_transition_time;
variable_2 : total_output_net_capacitance;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.3");
}
cell (INVX1) {
area : 0;
cell_leakage_power : 2.94349e-05;
pg_pin (vdd) {
voltage_name : "vdd";
}
pg_pin (vss) {
pg_type : primary_ground;
voltage_name : "vss";
}
leakage_power () {
value : 2.34926e-05;
when : "A";
related_pg_pin : vdd;
}
leakage_power () {
value : 0;
when : "A";
related_pg_pin : vss;
}
leakage_power () {
value : 3.53772e-05;
when : "!A";
related_pg_pin : vdd;
}
leakage_power () {
value : 0;
when : "!A";
related_pg_pin : vss;
}
leakage_power () {
value : 2.94349e-05;
related_pg_pin : vdd;
}
leakage_power () {
value : 0;
related_pg_pin : vss;
}
pin (Y) {
direction : output;
function : "!A";
power_down_function : "(!vdd) + (vss)";
related_ground_pin : vss;
related_power_pin : vdd;
max_capacitance : 0.0424924;
max_transition : 0.467016;
timing () {
related_pin : "A";
timing_sense : negative_unate;
timing_type : combinational;
cell_rise (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.00369357, 0.214289", \
"0.0507743, 0.381691" \
);
}
rise_transition (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.00503024, 0.436188", \
"0.062105, 0.467016" \
);
}
cell_fall (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.00319895, 0.174419", \
"0.0349018, 0.336763" \
);
}
fall_transition (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.00383817, 0.344531", \
"0.0623, 0.385021" \
);
}
}
internal_power () {
related_pin : "A";
related_pg_pin : vdd;
rise_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.000324845, 0.000254613", \
"0.000371345, 0.000180039" \
);
}
fall_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"7.22959e-06, 1.02158e-05", \
"4.97937e-05, 3.81527e-06" \
);
}
}
internal_power () {
related_pin : "A";
related_pg_pin : vss;
rise_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"-7.2684e-06, -3.36711e-06", \
"3.90183e-05, -1.43964e-05" \
);
}
fall_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.000340007, 0.000277934", \
"0.000382212, 0.000145537" \
);
}
}
}
pin (A) {
direction : input;
related_ground_pin : vss;
related_power_pin : vdd;
max_transition : 0.48;
capacitance : 0.000453208;
rise_capacitance : 0.000463735;
rise_capacitance_range (0.000395912, 0.000552107);
fall_capacitance : 0.000442681;
fall_capacitance_range (0.000368411, 0.000551596);
}
}
}