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Verilog Codes of all Gates

report timing commands for Tempus

set_propagated_clock [get_clocks clk]

# Timing Reports without source and network latency
puts "Timing Report for : 1"
report_timing -from [get_ports d_in] -to [get_pins q1_reg/D]
puts "Timing Report for : 2"
report_timing -from [get_pins q1_reg/CK] -to [get_pins q2_reg/D]
puts "Timing Report for : 3"
report_timing -from [get_pins q2_reg/CK] -to [get_ports q_out]
puts "Timing Report for : 4"
report_timing -from [get_ports d_in] -to [get_ports q_out]
puts "Timing Report for : 5"
report_timing -from [all_inputs] -to [all_registers]
puts "Timing Report for : 6"
report_timing -from [all_registers] -to [all_registers]
puts "Timing Report for : 7"
report_timing -from [all_registers] -to [all_outputs]
puts "Timing Report for : 8"
report_timing -from [all_inputs] -to [all_outputs]
puts "Timing Report for : 9"
report_timing -from [all_inputs] -to [all_registers]  -max_paths 10000
puts "Timing Report for : 10"
report_timing -from [all_registers] -to [all_registers]  -max_paths 10000
puts "Timing Report for : 11"
report_timing -from [all_registers] -to [all_outputs]  -max_paths 10000
puts "Timing Report for : 12"
report_timing -from [all_inputs] -to [all_outputs]  -max_paths 10000

# Timing Reports with source and network latency
report_timing -path_type end  
report_timing -path_type end_slack_only  
report_timing -path_type full  
report_timing -path_type full_clock  
report_timing -path_type summary  
report_timing -path_type summary_slack_only


#after applying derates i.e. OCV
report_delay_calculation -from g6/A -to g6/Y

# To see maximum number of paths that are getting violated 
report_timing -max_paths 10


#False Path 
set_false_path -from clk3 -to clk4

# To Reset the Constraints with out exiting the Tempus GUI
reset_sdc

# To create a generated clock sample command
create_generated_clock -divide_by 3 -source clk [get_pins g6/A]

# clk1 and clk2 are going as inputs to mux and output of this mux is driving two different flip flops they are synchronous but in report_timing it is showing differently
set_clock_groups -logically_exclusive -group clk1 -group -clk2


# Multi cycle path 
set_multicycle_path -setup 2 -through g6/Y
set_multicycle_path -hold 1 -through g6/Y

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