The commands get_clock, get_clock_ports, and get_clocks serve different purposes in the context of EDA tools like Cadence Genus. Here's a breakdown:
- get_clock: This command is typically used to retrieve a specific clock object by its name. It focuses on identifying and working with a single clock in the design.
- get_clock_ports: This command is used to find the clock ports of a design. Clock ports are the input points where clocks enter the design, and this command helps in identifying those specific ports.
- get_clocks: This command retrieves a collection of all clocks in the design. It provides options for filtering, using regular expressions, or making the search case-insensitive, making it useful for analyzing multiple clocks at once.
In summary:
- Use get_clock for a specific clock.
- Use get_clock_ports to identify clock input ports.
- Use get_clocks to retrieve and analyze all clocks in the design.
get_clock -help
@genus:root: 37> get_clock -help
Usage: get_clocks [-quiet] [-regexp] [-nocase] [-filter <string>] [<string>]
[-quiet]:
do not display any warning or error messages
[-regexp]:
indicates that the pattern is a regular expression
[-nocase]:
indicates that the pattern is not case sensitive
[-filter <string>]:
filters the collection with the specified expression
[<string>]:
clock names
@genus:root: 38>
get_clocks -help
@genus:root: 38> get_clocks -help
Usage: get_clocks [-quiet] [-regexp] [-nocase] [-filter <string>] [<string>]
[-quiet]:
do not display any warning or error messages
[-regexp]:
indicates that the pattern is a regular expression
[-nocase]:
indicates that the pattern is not case sensitive
[-filter <string>]:
filters the collection with the specified expression
[<string>]:
clock names
@genus:root: 39>
get_clock_ports -help
@genus:root: 39> get_clock_ports -help
get_clock_ports: finds clock ports of the design
Usage: get_clock_ports [<design>]
[<design>]:
target design
@genus:root: 40>
create_clock -help
Usage: create_clock [-add] [-name <string>] [-comment <string>] [-domain <string>] -period <float> [-waveform <float>+] [-apply_inverted <port|pin|hpin>+]
[<port|pin|hpin>+]
[-add]:
should the sources add or overwrite
[-name <string>]:
name of the clock
[-comment <string>]:
comment to be tagged with this command
[-domain <string>]:
name of the clock domain for the clock
-period <float>:
clock period
[-waveform <float>+]:
waveform string
[-apply_inverted <port|pin|hpin>+]:
sources of the clock that are inverted
[<port|pin|hpin>+]:
sources that are not inverted
Example:
@genus:root: 43> create_clock -name clk -period 4 -waveform {0 2} [get_port clk]
Info : Removed object. [TUI-58]
: Removed external_delay 'external_delay:counter/create_clock_delay_domain_1_clk_R_0'.
Info : Removed object. [TUI-58]
: Removed external_delay 'external_delay:counter/create_clock_delay_domain_1_clk_F_0'.
Warning : Replacing existing clock definition. [TIM-101]
: The clock name is 'clk'
Info : Replacing an existing timing exception with another. [TIM-304]
: Existing timing exception is 'path_groups/clk'.
@genus:root: 81> report_timing
Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'counter'.
============================================================
Generated by: Genus(TM) Synthesis Solution 17.22-s017_1
Generated on: Mar 27 2019 03:56:46 am
Module: counter
Operating conditions: PVT_0P9V_125C
Interconnect mode: global
Area mode: physical library
============================================================
Path 1: MET (1973 ps) Setup Check with Pin count_reg[7]/CK->D
Group: clk
Startpoint: (R) count_reg[1]/CK
Clock: (R) clk
Endpoint: (R) count_reg[7]/D
Clock: (R) clk
Capture Launch
Clock Edge:+ 4000 0
Src Latency:+ 0 0
Net Latency:+ 0 (I) 0 (I)
Arrival:= 4000 0
Setup:- 160
Required Time:= 3840
Launch Clock:- 0
Data Path:- 1867
Slack:= 1973
#----------------------------------------------------------------------------------------
# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance
# (fF) (ps) (ps) (ps) Location
#----------------------------------------------------------------------------------------
count_reg[1]/CK - - R (arrival) 7 - 0 - 0 (-,-)
count_reg[1]/Q - CK->Q R DFFRHQX1 3 11.0 240 353 353 (-,-)
g201__2683/Y - A->Y R AND2X1 1 4.5 109 268 620 (-,-)
g199__9682/CO - B->CO R ADDHX1 1 4.5 109 206 826 (-,-)
g197__4547/CO - B->CO R ADDHX1 1 4.5 109 206 1032 (-,-)
g195__1474/CO - B->CO R ADDHX1 1 4.5 109 206 1238 (-,-)
g193__3772/CO - B->CO R ADDHX1 1 4.5 109 206 1444 (-,-)
g191__4296/CO - B->CO R ADDHX1 1 4.3 105 204 1648 (-,-)
g189__8780/Y - B->Y R CLKXOR2X1 1 4.2 105 219 1867 (-,-)
count_reg[7]/D <<< - R DFFRHQX1 1 - - 0 1867 (-,-)
#----------------------------------------------------------------------------------------