Verilog Codes of all Gates

Verilog Modeling for Digital Logic Gates

In This post will walk you through the Verilog code for modeling various digital logic gates, covering level, data flow, and behavioral styles. Each gate will also include its CMOS representation and a truth table for better understanding.

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1. NOT Gate

Truth Table:

Truth Table	NOT
a	y
0	1
1	0

Gate Level Modeling:

module not_gate_level_modelling(y, a);
  output y;
  input a;
  not x1(y, a);
endmodule

Data Flow Modeling:

module not_data_flow_modelling(y, a);
  output y;
  input a;
  assign y = ~a;
endmodule

Behavioral Modeling:

module not_behavioural_modelling(y, a);
  output y;
  input a;
  reg y;
  always @(a)
    y = ~a;
endmodule

CMOS Representation: 

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2. AND Gate

Truth Table:

Truth Table		AND
a	b	y
0	0	0
0	1	0
1	0	0
1	1	1

Gate Level Modeling:

module and_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  and x1(y, a, b);
endmodule

Data Flow Modeling:

module and_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = a & b;
endmodule

Behavioral Modeling:

module and_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = a & b;
endmodule

CMOS Representation: 

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3. OR Gate

Truth Table:

Truth Table		OR
a	b	y
0	0	0
0	1	1
1	0	1
1	1	1

Gate Level Modeling:

module or_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  or x1(y, a, b);
endmodule

Data Flow Modeling:

module or_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = a | b;
endmodule

Behavioral Modeling:

module or_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = a | b;
endmodule

CMOS Representation: 

---

4. NAND Gate

Truth Table:

Truth Table		NAND
a	b	y
0	0	1
0	1	1
1	0	1
1	1	0

Gate Level Modeling:

module nand_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  nand x1(y, a, b);
endmodule

Data Flow Modeling:

module nand_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = ~(a & b);
endmodule

Behavioral Modeling:

module nand_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = ~(a & b);
endmodule

CMOS Representation: 

---

5. NOR Gate

Truth Table:

Truth Table		NOR
a	b	y
0	0	1
0	1	0
1	0	0
1	1	0

Gate Level Modeling:

module nor_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  nor x1(y, a, b);
endmodule

Data Flow Modeling:

module nor_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = ~(a | b);
endmodule

Behavioral Modeling:

module nor_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = ~(a | b);
endmodule

CMOS Representation: 

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6. XOR Gate

Truth Table:

Truth Table		XOR
a	b	y
0	0	0
0	1	1
1	0	1
1	1	0

Gate Level Modeling:

module xor_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  xor x1(y, a, b);
endmodule

Data Flow Modeling:

module xor_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = a ^ b;
endmodule

Behavioral Modeling:

module xor_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = a ^ b;
endmodule

CMOS Representation: [CMOS XOR Image]

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7. XNOR Gate

Truth Table:

Truth Table		XNOR
a	b	y
0	0	1
0	1	0
1	0	0
1	1	1

Gate Level Modeling:

module xnor_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  xnor x1(y, a, b);
endmodule

Data Flow Modeling:

module xnor_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = ~(a ^ b);
endmodule

Behavioral Modeling:

module xnor_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = ~(a ^ b);
endmodule

CMOS Representation: [CMOS XNOR Image]

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• YouTube: T Maharshi Sanand Yadav

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