180nm Circuit Description Languages of all Gates
NOT GATE:
************************************************************************ * auCdl Netlist: * * Library Name: inverter * Top Cell Name: inverter * View Name: schematic * Netlisted on: Mar 1 23:45:32 2023 ************************************************************************ *.BIPOLAR *.RESI = 2000 *.RESVAL *.CAPVAL *.DIOPERI *.DIOAREA *.EQUATION *.SCALE METER *.MEGA .PARAM ************************************************************************ * Library Name: inverter * Cell Name: inverter * View Name: schematic ************************************************************************ simulator lang=spice .SUBCKT inverter A GND VDD Y *.PININFO A:I Y:O GND:B VDD:B MNM0 Y A GND GND nmos W=2u L=180n M=1 MPM0 Y A VDD VDD pmos W=2u L=180n M=1 .ENDS
AND GATE:
************************************************************************ * auCdl Netlist: * * Library Name: and_gate * Top Cell Name: and * View Name: schematic * Netlisted on: Mar 1 23:00:46 2023 ************************************************************************ *.BIPOLAR *.RESI = 2000 *.RESVAL *.CAPVAL *.DIOPERI *.DIOAREA *.EQUATION *.SCALE METER *.MEGA .PARAM ************************************************************************ * Library Name: nand_gate * Cell Name: nand * View Name: schematic ************************************************************************ simulator lang=spice .SUBCKT nand A B GND VDD Y *.PININFO A:I B:I Y:O GND:B VDD:B MNM1 net20 B GND GND nmos W=2u L=180n M=1 MNM0 Y A net20 GND nmos W=2u L=180n M=1 MPM1 Y B VDD VDD pmos W=2u L=180n M=1 MPM0 Y A VDD VDD pmos W=2u L=180n M=1 .ENDS ************************************************************************ * Library Name: inverter * Cell Name: inverter * View Name: schematic ************************************************************************ .SUBCKT inverter A GND VDD Y *.PININFO A:I Y:O GND:B VDD:B MNM0 Y A GND GND nmos W=2u L=180n M=1 MPM0 Y A VDD VDD pmos W=2u L=180n M=1 .ENDS ************************************************************************ * Library Name: and_gate * Cell Name: and * View Name: schematic ************************************************************************ .SUBCKT and A B GND VDD Y *.PININFO A:I B:I Y:O GND:B VDD:B XI0 A B GND VDD net15 / nand XI1 net15 GND VDD Y / inverter .ENDS
OR GATE:
************************************************************************ * auCdl Netlist: * * Library Name: or_gate * Top Cell Name: or * View Name: schematic * Netlisted on: Mar 1 23:49:45 2023 ************************************************************************ *.BIPOLAR *.RESI = 2000 *.RESVAL *.CAPVAL *.DIOPERI *.DIOAREA *.EQUATION *.SCALE METER *.MEGA .PARAM ************************************************************************ * Library Name: nor_gate * Cell Name: nor * View Name: schematic ************************************************************************ simulator lang=spice .SUBCKT nor A B GND VDD Y *.PININFO A:I B:I Y:O GND:B VDD:B MNM1 Y B GND GND nmos W=2u L=180n M=1 MNM0 Y A GND GND nmos W=2u L=180n M=1 MPM1 net18 A VDD VDD pmos W=2u L=180n M=1 MPM0 Y B net18 VDD pmos W=2u L=180n M=1 .ENDS ************************************************************************ * Library Name: inverter * Cell Name: inverter * View Name: schematic ************************************************************************ .SUBCKT inverter A GND VDD Y *.PININFO A:I Y:O GND:B VDD:B MNM0 Y A GND GND nmos W=2u L=180n M=1 MPM0 Y A VDD VDD pmos W=2u L=180n M=1 .ENDS ************************************************************************ * Library Name: or_gate * Cell Name: or * View Name: schematic ************************************************************************ .SUBCKT or A B GND VDD Y *.PININFO A:I B:I Y:O GND:B VDD:B XI0 A B GND VDD net14 / nor XI1 net14 GND VDD Y / inverter .ENDS
NAND GATE:
************************************************************************ * auCdl Netlist: * * Library Name: nand_gate * Top Cell Name: nand * View Name: schematic * Netlisted on: Mar 1 23:47:43 2023 ************************************************************************ *.BIPOLAR *.RESI = 2000 *.RESVAL *.CAPVAL *.DIOPERI *.DIOAREA *.EQUATION *.SCALE METER *.MEGA .PARAM ************************************************************************ * Library Name: nand_gate * Cell Name: nand * View Name: schematic ************************************************************************ simulator lang=spice .SUBCKT nand A B GND VDD Y *.PININFO A:I B:I Y:O GND:B VDD:B MNM1 net20 B GND GND nmos W=2u L=180n M=1 MNM0 Y A net20 GND nmos W=2u L=180n M=1 MPM1 Y B VDD VDD pmos W=2u L=180n M=1 MPM0 Y A VDD VDD pmos W=2u L=180n M=1 .ENDS
NOR GATE:
************************************************************************ * auCdl Netlist: * * Library Name: nor_gate * Top Cell Name: nor * View Name: schematic * Netlisted on: Mar 1 23:48:13 2023 ************************************************************************ *.BIPOLAR *.RESI = 2000 *.RESVAL *.CAPVAL *.DIOPERI *.DIOAREA *.EQUATION *.SCALE METER *.MEGA .PARAM ************************************************************************ * Library Name: nor_gate * Cell Name: nor * View Name: schematic ************************************************************************ simulator lang=spice .SUBCKT nor A B GND VDD Y *.PININFO A:I B:I Y:O GND:B VDD:B MNM1 Y B GND GND nmos W=2u L=180n M=1 MNM0 Y A GND GND nmos W=2u L=180n M=1 MPM1 net18 A VDD VDD pmos W=2u L=180n M=1 MPM0 Y B net18 VDD pmos W=2u L=180n M=1 .ENDS
XOR GATE:
************************************************************************ * auCdl Netlist: * * Library Name: exor_gate * Top Cell Name: exor * View Name: schematic * Netlisted on: Mar 1 23:43:31 2023 ************************************************************************ *.BIPOLAR *.RESI = 2000 *.RESVAL *.CAPVAL *.DIOPERI *.DIOAREA *.EQUATION *.SCALE METER *.MEGA .PARAM ************************************************************************ * Library Name: inverter * Cell Name: inverter * View Name: schematic ************************************************************************ simulator lang=spice .SUBCKT inverter A GND VDD Y *.PININFO A:I Y:O GND:B VDD:B MNM0 Y A GND GND nmos W=2u L=180n M=1 MPM0 Y A VDD VDD pmos W=2u L=180n M=1 .ENDS ************************************************************************ * Library Name: exor_gate * Cell Name: exor * View Name: schematic ************************************************************************ .SUBCKT exor a b gnd vdd Y *.PININFO a:I b:I Y:O gnd:B vdd:B MPM5 Y b net23 vdd pmos W=2u L=180n M=1 MPM4 net23 abar vdd vdd pmos W=2u L=180n M=1 MPM1 Y bbar net24 vdd pmos W=2u L=180n M=1 MPM0 net24 a vdd vdd pmos W=2u L=180n M=1 MNM3 net21 bbar gnd gnd nmos W=2u L=180n M=1 MNM2 Y abar net21 gnd nmos W=2u L=180n M=1 MNM1 net22 b gnd gnd nmos W=2u L=180n M=1 MNM0 Y a net22 gnd nmos W=2u L=180n M=1 XI1 a gnd vdd abar / inverter XI0 b gnd vdd bbar / inverter .ENDS
XNOR GATE:
************************************************************************ * auCdl Netlist: * * Library Name: exnor_gate * Top Cell Name: exnor * View Name: schematic * Netlisted on: Mar 1 23:01:22 2023 ************************************************************************ *.BIPOLAR *.RESI = 2000 *.RESVAL *.CAPVAL *.DIOPERI *.DIOAREA *.EQUATION *.SCALE METER *.MEGA .PARAM ************************************************************************ * Library Name: inverter * Cell Name: inverter * View Name: schematic ************************************************************************ simulator lang=spice .SUBCKT inverter A GND VDD Y *.PININFO A:I Y:O GND:B VDD:B MNM0 Y A GND GND nmos W=2u L=180n M=1 MPM0 Y A VDD VDD pmos W=2u L=180n M=1 .ENDS ************************************************************************ * Library Name: exor_gate * Cell Name: exor * View Name: schematic ************************************************************************ .SUBCKT exor a b gnd vdd Y *.PININFO a:I b:I Y:O gnd:B vdd:B MPM5 Y b net23 vdd pmos W=2u L=180n M=1 MPM4 net23 abar vdd vdd pmos W=2u L=180n M=1 MPM1 Y bbar net24 vdd pmos W=2u L=180n M=1 MPM0 net24 a vdd vdd pmos W=2u L=180n M=1 MNM3 net21 bbar gnd gnd nmos W=2u L=180n M=1 MNM2 Y abar net21 gnd nmos W=2u L=180n M=1 MNM1 net22 b gnd gnd nmos W=2u L=180n M=1 MNM0 Y a net22 gnd nmos W=2u L=180n M=1 XI1 a gnd vdd abar / inverter XI0 b gnd vdd bbar / inverter .ENDS ************************************************************************ * Library Name: exnor_gate * Cell Name: exnor * View Name: schematic ************************************************************************ .SUBCKT exnor A B GND VDD Y *.PININFO A:I B:I Y:O GND:B VDD:B XI0 A B GND VDD net14 / exor XI1 net14 GND VDD Y / inverter .ENDS