TMSY Tutorials: 04/14/25

Verilog Codes of all Gates

Verilog Modeling for Digital Logic Gates

In This post will walk you through the Verilog code for modeling various digital logic gates, covering level, data flow, and behavioral styles. Each gate will also include its CMOS representation and a truth table for better understanding.

1. NOT Gate

Truth Table:

Truth Table	NOT
a	y
0	1
1	0

Gate Level Modeling:

module not_gate_level_modelling(y, a);
  output y;
  input a;
  not x1(y, a);
endmodule

Data Flow Modeling:

module not_data_flow_modelling(y, a);
  output y;
  input a;
  assign y = ~a;
endmodule

Behavioral Modeling:

module not_behavioural_modelling(y, a);
  output y;
  input a;
  reg y;
  always @(a)
    y = ~a;
endmodule

CMOS Representation:

2. AND Gate

Truth Table:

Truth Table		AND
a	b	y
0	0	0
0	1	0
1	0	0
1	1	1

Gate Level Modeling:

module and_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  and x1(y, a, b);
endmodule

Data Flow Modeling:

module and_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = a & b;
endmodule

Behavioral Modeling:

module and_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = a & b;
endmodule

CMOS Representation:

3. OR Gate

Truth Table:

Truth Table		OR
a	b	y
0	0	0
0	1	1
1	0	1
1	1	1

Gate Level Modeling:

module or_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  or x1(y, a, b);
endmodule

Data Flow Modeling:

module or_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = a | b;
endmodule

Behavioral Modeling:

module or_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = a | b;
endmodule

CMOS Representation:

4. NAND Gate

Truth Table:

Truth Table		NAND
a	b	y
0	0	1
0	1	1
1	0	1
1	1	0

Gate Level Modeling:

module nand_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  nand x1(y, a, b);
endmodule

Data Flow Modeling:

module nand_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = ~(a & b);
endmodule

Behavioral Modeling:

module nand_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = ~(a & b);
endmodule

CMOS Representation:

5. NOR Gate

Truth Table:

Truth Table		NOR
a	b	y
0	0	1
0	1	0
1	0	0
1	1	0

Gate Level Modeling:

module nor_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  nor x1(y, a, b);
endmodule

Data Flow Modeling:

module nor_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = ~(a | b);
endmodule

Behavioral Modeling:

module nor_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = ~(a | b);
endmodule

CMOS Representation:

6. XOR Gate

Truth Table:

Truth Table		XOR
a	b	y
0	0	0
0	1	1
1	0	1
1	1	0

Gate Level Modeling:

module xor_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  xor x1(y, a, b);
endmodule

Data Flow Modeling:

module xor_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = a ^ b;
endmodule

Behavioral Modeling:

module xor_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = a ^ b;
endmodule

CMOS Representation: [CMOS XOR Image]

7. XNOR Gate

Truth Table:

Truth Table		XNOR
a	b	y
0	0	1
0	1	0
1	0	0
1	1	1

Gate Level Modeling:

module xnor_gate_level_modelling(y, a, b);
  output y;
  input a, b;
  xnor x1(y, a, b);
endmodule

Data Flow Modeling:

module xnor_data_flow_modelling(y, a, b);
  output y;
  input a, b;
  assign y = ~(a ^ b);
endmodule

Behavioral Modeling:

module xnor_behavioural_modelling(y, a, b);
  output y;
  input a, b;
  reg y;
  always @(a or b)
    y = ~(a ^ b);
endmodule

CMOS Representation: [CMOS XNOR Image]

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Here's a guide for Prism.js, which is lightweight and easy to integrate into your Blogger site:

Step 1: Add Prism.js to Your Blogger Site

Go to Blogger Dashboard → Theme → Customize → Advanced → Add CSS.
In the Add CSS section, add the following code to include Prism.js:

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Go to Blogger Dashboard → Theme → Edit HTML.
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    input b,
    output c
);
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endmodule
</code></pre>

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.static_page .post {

width: 100% !important;

max-width: 100% !important;

margin: 0 auto !important;

padding: 30px !important;

box-sizing: border-box;

background: white;

box-shadow: 0 2px 10px rgba(0,0,0,0.1);

background-color: #ffffff !important; /* Ensures the background is white */

width: 100% !important; /* Ensures full width */

padding: 20px; /* Adds spacing around the content */

border: none; /* Removes any border around the content */

box-shadow: none; /* Removes shadow effects, if present */

}

/* 2. Disable animation transitions */

body *,

body *::before,

body *::after {

animation: none !important;

transition: none !important;

}

/* 3. Make background consistent */

body {

background-color: #ffffff !important; /* Ensures the background is white */

}

/* 4. Hide unwanted transitions or dynamic view effects */

#header-container,

#content,

#footer,

.dynamic-view,

.content-outer,

.content-fauxcolumn-outer,

.main-outer {

animation: none !important;

transition: none !important;

}

/* 5. Disable dynamic resize flicker */

iframe, embed, object {

max-width: 100%;

}

img {

border: none !important; /* Removes any borders around images */

box-shadow: none !important; /* Removes outer box/shadow effects */

padding: 0; /* Ensures no padding around the image */

margin: 0; /* Removes any margin around the image */

}

.menu-bar {

background-color: #000000 !important; /* Dark black background */

font-weight: bold !important; /* Bold font for text */

color: #ffffff !important; /* White font color for contrast */

}

.menu-bar a {

text-decoration: none; /* Removes underlines from menu links */

color: #ffffff !important; /* Ensures links in the menu are white */

}

.menu-bar li {

display: inline-block; /* Ensures menu items are displayed inline */

padding: 10px 20px; /* Adjust spacing between items */

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DFFX1

DFFX1 - NLDM 


library (TT_25_1.1) {
  /* Models written by Liberate dev from Cadence Design Systems, Inc. on Mon Mar 25 04:36:21 IST 2019 */
  comment : "";
  date : "$Date: Mon Mar 25 04:33:29 2019 $";
  revision : "1.0";
  delay_model : table_lookup;
  capacitive_load_unit (1,pf);
  current_unit : "1mA";
  leakage_power_unit : "1uW";
  pulling_resistance_unit : "1kohm";
  time_unit : "1ns";
  voltage_unit : "1V";
  voltage_map (VDD, 1.1);
  voltage_map (VSS, 0);
  voltage_map (VNW, 1.1);
  voltage_map (VPW, 0);
  voltage_map (GND, 0);
  default_cell_leakage_power : 0;
  default_fanout_load : 1;
  default_max_transition : 0.48;
  default_output_pin_cap : 0;
  in_place_swap_mode : match_footprint;
  input_threshold_pct_fall : 50;
  input_threshold_pct_rise : 50;
  nom_process : 1;
  nom_temperature : 25;
  nom_voltage : 1.1;
  output_threshold_pct_fall : 50;
  output_threshold_pct_rise : 50;
  slew_derate_from_library : 0.5;
  slew_lower_threshold_pct_fall : 30;
  slew_lower_threshold_pct_rise : 30;
  slew_upper_threshold_pct_fall : 70;
  slew_upper_threshold_pct_rise : 70;
  operating_conditions (PVT_1P1V_25C) {
    process : 1;
    temperature : 25;
    voltage : 1.1;
  }
  default_operating_conditions : PVT_1P1V_25C;
  lu_table_template (constraint_template_2x2) {
    variable_1 : constrained_pin_transition;
    variable_2 : related_pin_transition;
    index_1 ("0.008, 0.28");
    index_2 ("0.008, 0.28");
  }
  lu_table_template (delay_template_2x2) {
    variable_1 : input_net_transition;
    variable_2 : total_output_net_capacitance;
    index_1 ("0.008, 0.28");
    index_2 ("0.01, 0.3");
  }
  lu_table_template (mpw_constraint_template_2x2) {
    variable_1 : constrained_pin_transition;
    index_1 ("0.008, 0.28");
  }
  power_lut_template (passive_power_template_2x1) {
    variable_1 : input_transition_time;
    index_1 ("0.008, 0.28");
  }
  power_lut_template (power_template_2x2) {
    variable_1 : input_transition_time;
    variable_2 : total_output_net_capacitance;
    index_1 ("0.008, 0.28");
    index_2 ("0.01, 0.3");
  }
  cell (DFFX1) {
    area : 0;
    cell_leakage_power : 5.28413e-05;
    pg_pin (VDD) {
      pg_type : primary_power;
      voltage_name : "VDD";
    }
    pg_pin (VSS) {
      pg_type : primary_ground;
      voltage_name : "VSS";
    }
    leakage_power () {
      value : 0;
      when : "CK * D";
      related_pg_pin : VDD;
    }
    leakage_power () {
      value : 0;
      when : "CK * !D";
      related_pg_pin : VDD;
    }
    leakage_power () {
      value : 0.000211365;
      when : "!CK * D";
      related_pg_pin : VDD;
    }
    leakage_power () {
      value : 0;
      when : "!CK * D";
      related_pg_pin : VSS;
    }
    leakage_power () {
      value : 0;
      when : "!CK * !D";
      related_pg_pin : VDD;
    }
    pin (Q) {
      direction : output;
      function : "IQ";
      power_down_function : "(!VDD) + (VSS)";
      related_ground_pin : VSS;
      related_power_pin : VDD;
      max_capacitance : 0.0516726;
      max_transition : 0.469635;
      timing () {
        related_pin : "CK";
        timing_sense : non_unate;
        timing_type : rising_edge;
        cell_rise (delay_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0516726");
          values ( \
            "0.0517316, 0.311286", \
            "0.132518, 0.392065" \
          );
        }
        rise_transition (delay_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0516726");
          values ( \
            "0.00813102, 0.469635", \
            "0.0082138, 0.469557" \
          );
        }
        cell_fall (delay_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0516726");
          values ( \
            "0.0572689, 0.269881", \
            "0.134867, 0.347662" \
          );
        }
        fall_transition (delay_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0516726");
          values ( \
            "0.0074735, 0.380366", \
            "0.007468, 0.380871" \
          );
        }
      }
      internal_power () {
        related_pin : "CK";
        related_pg_pin : VDD;
        rise_power (power_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0516726");
          values ( \
            "0.000606113, 0.000592962", \
            "0.000597266, 0.000592315" \
          );
        }
        fall_power (power_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0516726");
          values ( \
            "0.000629339, 0.000582196", \
            "0.000640112, 0.000605796" \
          );
        }
      }
      internal_power () {
        related_pin : "CK";
        related_pg_pin : VSS;
        rise_power (power_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0516726");
          values ( \
            "0.000605979, 0.000634574", \
            "0.000597074, 0.000622664" \
          );
        }
        fall_power (power_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0516726");
          values ( \
            "0.000631061, 0.000633563", \
            "0.000642016, 0.00064652" \
          );
        }
      }
    }
    pin (QN) {
      direction : output;
      function : "IQN";
      power_down_function : "(!VDD) + (VSS)";
      related_ground_pin : VSS;
      related_power_pin : VDD;
      max_capacitance : 0.0523145;
      max_transition : 0.475785;
      timing () {
        related_pin : "CK";
        timing_sense : non_unate;
        timing_type : rising_edge;
        cell_rise (delay_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0523145");
          values ( \
            "0.0699707, 0.32933", \
            "0.147575, 0.406816" \
          );
        }
        rise_transition (delay_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0523145");
          values ( \
            "0.00642612, 0.475697", \
            "0.0064258, 0.475785" \
          );
        }
        cell_fall (delay_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0523145");
          values ( \
            "0.064953, 0.2765", \
            "0.145779, 0.357277" \
          );
        }
        fall_transition (delay_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0523145");
          values ( \
            "0.00593988, 0.384826", \
            "0.0059468, 0.384798" \
          );
        }
      }
      internal_power () {
        related_pin : "CK";
        related_pg_pin : VDD;
        rise_power (power_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0523145");
          values ( \
            "0.000629268, 0.000617817", \
            "0.000640319, 0.000634569" \
          );
        }
        fall_power (power_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0523145");
          values ( \
            "0.000605939, 0.00056227", \
            "0.000596922, 0.000568011" \
          );
        }
      }
      internal_power () {
        related_pin : "CK";
        related_pg_pin : VSS;
        rise_power (power_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0523145");
          values ( \
            "0.000631447, 0.000654515", \
            "0.000642621, 0.000672219" \
          );
        }
        fall_power (power_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0001, 0.0523145");
          values ( \
            "0.000605351, 0.000609879", \
            "0.000596287, 0.000602476" \
          );
        }
      }
    }
    pin (CK) {
      clock : true;
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      max_transition : 0.48;
      capacitance : 0.000268552;
      rise_capacitance : 0.000271016;
      rise_capacitance_range (0.000235053, 0.000306786);
      fall_capacitance : 0.000266088;
      fall_capacitance_range (0.000226229, 0.000305946);
      timing () {
        related_pin : "CK";
        sdf_cond : "adacond_D == 1'b1";
        timing_type : min_pulse_width;
        when : "D";
        rise_constraint (mpw_constraint_template_2x2) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.0312042, 0.480957" \
          );
        }
        fall_constraint (mpw_constraint_template_2x2) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.0387001, 0.480957" \
          );
        }
      }
      timing () {
        related_pin : "CK";
        sdf_cond : "adacond_NOT_D == 1'b1";
        timing_type : min_pulse_width;
        when : "!D";
        rise_constraint (mpw_constraint_template_2x2) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.0312042, 0.480957" \
          );
        }
        fall_constraint (mpw_constraint_template_2x2) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.046196, 0.480957" \
          );
        }
      }
      internal_power () {
        when : "D";
        related_pg_pin : VDD;
        rise_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000424685, 0.000433129" \
          );
        }
        fall_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000628956, 0.000639238" \
          );
        }
      }
      internal_power () {
        when : "D";
        related_pg_pin : VSS;
        rise_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000607546, 0.0006154" \
          );
        }
        fall_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000449656, 0.000459933" \
          );
        }
      }
      internal_power () {
        when : "!D";
        related_pg_pin : VDD;
        rise_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000405546, 0.000414972" \
          );
        }
        fall_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000645044, 0.000654927" \
          );
        }
      }
      internal_power () {
        when : "!D";
        related_pg_pin : VSS;
        rise_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.00059296, 0.000601631" \
          );
        }
        fall_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000456382, 0.000466362" \
          );
        }
      }
    }
    pin (D) {
      direction : input;
      related_ground_pin : VSS;
      related_power_pin : VDD;
      max_transition : 0.48;
      capacitance : 0.000246968;
      rise_capacitance : 0.000248464;
      rise_capacitance_range (0.000232892, 0.000264036);
      fall_capacitance : 0.000245471;
      fall_capacitance_range (0.00022608, 0.000264863);
      timing () {
        related_pin : "CK";
        timing_type : hold_rising;
        rise_constraint (constraint_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0004, 0.48");
          values ( \
            "1e+31, 1e+31", \
            "1e+31, 1e+31" \
          );
        }
        fall_constraint (constraint_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0004, 0.48");
          values ( \
            "0, 0.063238", \
            "-0.0739072, -0.0137963" \
          );
        }
      }
      timing () {
        related_pin : "CK";
        timing_type : setup_rising;
        rise_constraint (constraint_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0004, 0.48");
          values ( \
            "0.0292976, -0.00376459", \
            "0.119711, 0.0678955" \
          );
        }
        fall_constraint (constraint_template_2x2) {
          index_1 ("0.0004, 0.48");
          index_2 ("0.0004, 0.48");
          values ( \
            "0.0251818, -0.0533258", \
            "0.123667, 0.0402344" \
          );
        }
      }
      internal_power () {
        when : "CK";
        related_pg_pin : VDD;
        rise_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "-6.53123e-05, -8.10531e-05" \
          );
        }
        fall_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "9.99081e-05, 0.00010092" \
          );
        }
      }
      internal_power () {
        when : "CK";
        related_pg_pin : VSS;
        rise_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "8.14506e-05, 6.72245e-05" \
          );
        }
        fall_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "-4.59516e-05, -4.64161e-05" \
          );
        }
      }
      internal_power () {
        when : "!CK";
        related_pg_pin : VDD;
        rise_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000519561, 0.000502595" \
          );
        }
        fall_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000709409, 0.000697475" \
          );
        }
      }
      internal_power () {
        when : "!CK";
        related_pg_pin : VSS;
        rise_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000696068, 0.000678888" \
          );
        }
        fall_power (passive_power_template_2x1) {
          index_1 ("0.0004, 0.48");
          values ( \
            "0.000533357, 0.000520657" \
          );
        }
      }
    }
    ff (IQ,IQN) {
      clocked_on : "CK";
      next_state : "D";
      power_down_function : "(!VDD) + (VSS)";
    }
  }
}

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Verilog Codes of all Gates

Verilog Codes of all Gates

Verilog Modeling for Digital Logic Gates

1. NOT Gate

Gate Level Modeling:

Data Flow Modeling:

Behavioral Modeling:

2. AND Gate

Gate Level Modeling:

Data Flow Modeling:

Behavioral Modeling:

3. OR Gate

Gate Level Modeling:

Data Flow Modeling:

Behavioral Modeling:

4. NAND Gate

Gate Level Modeling:

Data Flow Modeling:

Behavioral Modeling:

5. NOR Gate

Gate Level Modeling:

Data Flow Modeling:

Behavioral Modeling:

6. XOR Gate

Gate Level Modeling:

Data Flow Modeling:

Behavioral Modeling:

7. XNOR Gate

Gate Level Modeling:

Data Flow Modeling:

Behavioral Modeling:

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