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Verilog Codes of all Gates
INVX1 NLDM VS LVF
INVX1 NLDM VS LVF
library (TT_25_1.1) {
/* Models written by Liberate dev from Cadence Design Systems, Inc. on Fri Feb 22 23:00:46 IST 2019 */
comment : "";
date : "$Date: Fri Feb 22 23:00:27 2019 $";
revision : "1.0";
delay_model : table_lookup;
capacitive_load_unit (1,pf);
current_unit : "1mA";
leakage_power_unit : "1uW";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
voltage_map (vdd, 1.1);
voltage_map (vss, 0);
voltage_map (vnw, 1.1);
voltage_map (vpw, 0);
voltage_map (GND, 0);
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_max_transition : 0.48;
default_output_pin_cap : 0;
in_place_swap_mode : match_footprint;
input_threshold_pct_fall : 50;
input_threshold_pct_rise : 50;
nom_process : 1;
nom_temperature : 25;
nom_voltage : 1.1;
output_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
slew_derate_from_library : 1;
slew_lower_threshold_pct_fall : 10;
slew_lower_threshold_pct_rise : 10;
slew_upper_threshold_pct_fall : 90;
slew_upper_threshold_pct_rise : 90;
operating_conditions (PVT_1P1V_25C) {
process : 1;
temperature : 25;
voltage : 1.1;
}
default_operating_conditions : PVT_1P1V_25C;
lu_table_template (constraint_template_2x2) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("0.008, 0.28");
index_2 ("0.008, 0.28");
}
lu_table_template (delay_template_2x2) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.3");
}
lu_table_template (mpw_constraint_template_2x2) {
variable_1 : constrained_pin_transition;
index_1 ("0.008, 0.28");
}
power_lut_template (passive_power_template_2x1) {
variable_1 : input_transition_time;
index_1 ("0.008, 0.28");
}
power_lut_template (power_template_2x2) {
variable_1 : input_transition_time;
variable_2 : total_output_net_capacitance;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.3");
}
cell (INVX1) {
area : 0;
cell_leakage_power : 2.94349e-05;
pg_pin (vdd) {
pg_type : primary_power;
voltage_name : "vdd";
}
pg_pin (vss) {
pg_type : primary_ground;
voltage_name : "vss";
}
leakage_power () {
value : 2.34926e-05;
when : "A";
related_pg_pin : vdd;
}
leakage_power () {
value : 0;
when : "A";
related_pg_pin : vss;
}
leakage_power () {
value : 3.53772e-05;
when : "!A";
related_pg_pin : vdd;
}
leakage_power () {
value : 0;
when : "!A";
related_pg_pin : vss;
}
leakage_power () {
value : 2.94349e-05;
related_pg_pin : vdd;
}
leakage_power () {
value : 0;
related_pg_pin : vss;
}
pin (Y) {
direction : output;
function : "!A";
power_down_function : "(!vdd) + (vss)";
related_ground_pin : vss;
related_power_pin : vdd;
max_capacitance : 0.0424924;
max_transition : 0.467016;
timing () {
related_pin : "A";
timing_sense : negative_unate;
timing_type : combinational;
cell_rise (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.00369357, 0.214289", \
"0.0507743, 0.381691" \
);
}
rise_transition (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.00503024, 0.436188", \
"0.062105, 0.467016" \
);
}
cell_fall (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.00319895, 0.174419", \
"0.0349018, 0.336763" \
);
}
fall_transition (delay_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.00383817, 0.344531", \
"0.0623, 0.385021" \
);
}
}
internal_power () {
related_pin : "A";
related_pg_pin : vdd;
rise_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.000324845, 0.000254613", \
"0.000371345, 0.000180039" \
);
}
fall_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"7.22959e-06, 1.02158e-05", \
"4.97937e-05, 3.81527e-06" \
);
}
}
internal_power () {
related_pin : "A";
related_pg_pin : vss;
rise_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"-7.2684e-06, -3.36711e-06", \
"3.90183e-05, -1.43964e-05" \
);
}
fall_power (power_template_2x2) {
index_1 ("0.0004, 0.48");
index_2 ("0.0001, 0.0424924");
values ( \
"0.000340007, 0.000277934", \
"0.000382212, 0.000145537" \
);
}
}
}
pin (A) {
direction : input;
related_ground_pin : vss;
related_power_pin : vdd;
max_transition : 0.48;
capacitance : 0.000453208;
rise_capacitance : 0.000463735;
rise_capacitance_range (0.000395912, 0.000552107);
fall_capacitance : 0.000442681;
fall_capacitance_range (0.000368411, 0.000551596);
}
}
}
library (TT_25_1.0) {
/* Models written by Variety dev from Cadence Design Systems, Inc. on Fri Feb 22 22:58:12 IST 2019 */
comment : "";
date : "$Date: Fri Feb 22 22:57:26 2019 $";
revision : "1.0";
delay_model : table_lookup;
capacitive_load_unit (1,pf);
current_unit : "1mA";
leakage_power_unit : "1uW";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
voltage_map (VDD, 1);
voltage_map (VSS, 0);
voltage_map (VNW, 1);
voltage_map (VPW, 0);
voltage_map (GND, 0);
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_max_transition : 0.48;
default_output_pin_cap : 0;
in_place_swap_mode : match_footprint;
input_threshold_pct_fall : 50;
input_threshold_pct_rise : 50;
nom_process : 1;
nom_temperature : 25;
nom_voltage : 1;
output_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
slew_derate_from_library : 0.5;
slew_lower_threshold_pct_fall : 30;
slew_lower_threshold_pct_rise : 30;
slew_upper_threshold_pct_fall : 70;
slew_upper_threshold_pct_rise : 70;
operating_conditions (PVT_1V_25C) {
process : 1;
temperature : 25;
voltage : 1;
}
default_operating_conditions : PVT_1V_25C;
lu_table_template (constraint_template_2x2) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("0.008, 0.28");
index_2 ("0.008, 0.28");
}
lu_table_template (delay_template_2x2) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.3");
}
lu_table_template (mpw_constraint_template_2x2) {
variable_1 : constrained_pin_transition;
index_1 ("0.008, 0.28");
}
power_lut_template (passive_power_template_2x1) {
variable_1 : input_transition_time;
index_1 ("0.008, 0.28");
}
power_lut_template (power_template_2x2) {
variable_1 : input_transition_time;
variable_2 : total_output_net_capacitance;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.3");
}
define_group(ocv_mean_shift_cell_rise, timing);
define_group(ocv_std_dev_cell_rise, timing);
define_group(ocv_skewness_cell_rise, timing);
define_group(ocv_mean_shift_rise_transition, timing);
define_group(ocv_std_dev_rise_transition, timing);
define_group(ocv_skewness_rise_transition, timing);
define_group(ocv_mean_shift_cell_fall, timing);
define_group(ocv_std_dev_cell_fall, timing);
define_group(ocv_skewness_cell_fall, timing);
define_group(ocv_mean_shift_fall_transition, timing);
define_group(ocv_std_dev_fall_transition, timing);
define_group(ocv_skewness_fall_transition, timing);
define_group(ocv_mean_shift_rise_constraint, timing);
define_group(ocv_std_dev_rise_constraint, timing);
define_group(ocv_skewness_rise_constraint, timing);
define_group(ocv_mean_shift_fall_constraint, timing);
define_group(ocv_std_dev_fall_constraint, timing);
define_group(ocv_skewness_fall_constraint, timing);
define(index_1, ocv_mean_shift_cell_rise, string);
define(index_2, ocv_mean_shift_cell_rise, string);
define(values, ocv_mean_shift_cell_rise, string);
define(index_1, ocv_std_dev_cell_rise, string);
define(index_2, ocv_std_dev_cell_rise, string);
define(values, ocv_std_dev_cell_rise, string);
define(index_1, ocv_skewness_cell_rise, string);
define(index_2, ocv_skewness_cell_rise, string);
define(values, ocv_skewness_cell_rise, string);
define(index_1, ocv_mean_shift_rise_transition, string);
define(index_2, ocv_mean_shift_rise_transition, string);
define(values, ocv_mean_shift_rise_transition, string);
define(index_1, ocv_std_dev_rise_transition, string);
define(index_2, ocv_std_dev_rise_transition, string);
define(values, ocv_std_dev_rise_transition, string);
define(index_1, ocv_skewness_rise_transition, string);
define(index_2, ocv_skewness_rise_transition, string);
define(values, ocv_skewness_rise_transition, string);
define(index_1, ocv_mean_shift_cell_fall, string);
define(index_2, ocv_mean_shift_cell_fall, string);
define(values, ocv_mean_shift_cell_fall, string);
define(index_1, ocv_std_dev_cell_fall, string);
define(index_2, ocv_std_dev_cell_fall, string);
define(values, ocv_std_dev_cell_fall, string);
define(index_1, ocv_skewness_cell_fall, string);
define(index_2, ocv_skewness_cell_fall, string);
define(values, ocv_skewness_cell_fall, string);
define(index_1, ocv_mean_shift_fall_transition, string);
define(index_2, ocv_mean_shift_fall_transition, string);
define(values, ocv_mean_shift_fall_transition, string);
define(index_1, ocv_std_dev_fall_transition, string);
define(index_2, ocv_std_dev_fall_transition, string);
define(values, ocv_std_dev_fall_transition, string);
define(index_1, ocv_skewness_fall_transition, string);
define(index_2, ocv_skewness_fall_transition, string);
define(values, ocv_skewness_fall_transition, string);
define(index_1, ocv_mean_shift_rise_constraint, string);
define(index_2, ocv_mean_shift_rise_constraint, string);
define(values, ocv_mean_shift_rise_constraint, string);
define(index_1, ocv_std_dev_rise_constraint, string);
define(index_2, ocv_std_dev_rise_constraint, string);
define(values, ocv_std_dev_rise_constraint, string);
define(index_1, ocv_skewness_rise_constraint, string);
define(index_2, ocv_skewness_rise_constraint, string);
define(values, ocv_skewness_rise_constraint, string);
define(index_1, ocv_mean_shift_fall_constraint, string);
define(index_2, ocv_mean_shift_fall_constraint, string);
define(values, ocv_mean_shift_fall_constraint, string);
define(index_1, ocv_std_dev_fall_constraint, string);
define(index_2, ocv_std_dev_fall_constraint, string);
define(values, ocv_std_dev_fall_constraint, string);
define(index_1, ocv_skewness_fall_constraint, string);
define(index_2, ocv_skewness_fall_constraint, string);
define(values, ocv_skewness_fall_constraint, string);
cell (INVX1) {
area : 0.684;
pg_pin (VDD) {
pg_type : primary_power;
voltage_name : "VDD";
}
pg_pin (VSS) {
pg_type : primary_ground;
voltage_name : "VSS";
}
pin (Y) {
direction : "output";
function : "!A";
power_down_function : "(!VDD) + (VSS)";
related_ground_pin : VSS;
related_power_pin : VDD;
max_capacitance : 0.25;
max_transition : 2.70797;
timing () {
related_pin : "A";
timing_sense : negative_unate;
timing_type : combinational;
ocv_mean_shift_cell_rise (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"9.5576e-05, 0.00224674, \
-1.39922e-05, 0.00264323";
}
ocv_std_dev_cell_rise (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"0.00242236, 0.0562067, \
0.00440192, 0.0575361";
}
ocv_skewness_cell_rise (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"0.600486, 0.603226, \
0.27273, 0.612578";
}
ocv_sigma_cell_rise (delay_template_2x2) {
sigma_type : early;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.25");
values ( \
"0.00212475, 0.0491915", \
"0.00438899, 0.0500194" \
);
}
ocv_sigma_cell_rise (delay_template_2x2) {
sigma_type : late;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.25");
values ( \
"0.00266391, 0.0618663", \
"0.00444717, 0.063538" \
);
}
ocv_mean_shift_rise_transition (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"0.000172578, 0.00417829, \
0.00017304, 0.00372291";
}
ocv_std_dev_rise_transition (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"0.0041212, 0.0995231, \
0.00165354, 0.099379";
}
ocv_skewness_rise_transition (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"0.609738, 0.611309, \
0.909093, 0.59703";
}
ocv_sigma_rise_transition (delay_template_2x2) {
sigma_type : early;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.25");
values ( \
"0.00359261, 0.0866381", \
"0.00111236, 0.0870802" \
);
}
ocv_sigma_rise_transition (delay_template_2x2) {
sigma_type : late;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.25");
values ( \
"0.0045525, 0.109996", \
"0.00234349, 0.108982" \
);
}
ocv_mean_shift_cell_fall (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"4.62346e-05, 0.00108528, \
4.73261e-05, 0.00159681";
}
ocv_std_dev_cell_fall (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"0.00132379, 0.0304232, \
0.00313214, 0.0303383";
}
ocv_skewness_cell_fall (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"0.557441, 0.560809, \
0.362727, 0.605576";
}
ocv_sigma_cell_fall (delay_template_2x2) {
sigma_type : early;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.25");
values ( \
"0.00121088, 0.0277619", \
"0.00306118, 0.0271202" \
);
}
ocv_sigma_cell_fall (delay_template_2x2) {
sigma_type : late;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.25");
values ( \
"0.00144149, 0.0332556", \
"0.00319825, 0.0338782" \
);
}
ocv_mean_shift_fall_transition (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"8.443e-05, 0.00204158, \
0.000131458, 0.00213146";
}
ocv_std_dev_fall_transition (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"0.00232723, 0.0562337, \
0.000429086, 0.0562071";
}
ocv_skewness_fall_transition (delay_template_2x2) {
index_1 : "0.008, 0.28";
index_2 : "0.01, 0.25";
values : \
"0.565736, 0.564995, \
0.675064, 0.5682";
}
ocv_sigma_fall_transition (delay_template_2x2) {
sigma_type : early;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.25");
values ( \
"0.00211985, 0.0512689", \
"0.000317894, 0.0511538" \
);
}
ocv_sigma_fall_transition (delay_template_2x2) {
sigma_type : late;
index_1 ("0.008, 0.28");
index_2 ("0.01, 0.25");
values ( \
"0.00254247, 0.0614752", \
"0.000547107, 0.0615664" \
);
}
}
}
pin (A) {
direction : "input";
related_ground_pin : VSS;
related_power_pin : VDD;
max_transition : 0.28;
capacitance : 0.000493376;
rise_capacitance : 0.000493376;
rise_capacitance_range (0.000418848, 0.000493376);
fall_capacitance : 0.000470286;
fall_capacitance_range (0.000401011, 0.000470286);
}
}
}
NLDM INVX1 .lib
NLDM + LVF INVX1 .lib
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